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George Hotz 2021-06-15 22:41:41 -07:00
commit 2f91c012eb
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1
extra/risk.py
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@ -152,6 +152,7 @@ binops = {BinaryOps.ADD: riski_add,
BinaryOps.POW: riski_pow}
@count
# TODO: add masks to matmul instruction?
def riski_matmul():
#print("LLL:\n",regfile[Reg.MATMUL_INPUT],"\n",regfile[Reg.MATMUL_WEIGHTS])
regfile[Reg.MATMUL_OUTPUT] += \

1
fpga/build.sh
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@ -11,6 +11,7 @@ $BASE/yosys/yosys -p "synth_xilinx -flatten -nowidelut -abc9 -arch xc7 -top top;
# nextpnr-xilinx 0be5cc19f3261101730ce9274720aaf3784f83e2
# cmake -DARCH=xilinx -DBUILD_GUI=no -DBUILD_PYTHON=no -DUSE_OPENMP=No .
# git submodule init && git submodule update
# python3 xilinx/python/bbaexport.py --device xc7a100tcsg324-1 --bba xilinx/xc7a100t.bba
# ./bbasm -l xilinx/xc7a100t.bba xilinx/xc7a100t.bin
$BASE/nextpnr-xilinx/nextpnr-xilinx --chipdb $BASE/nextpnr-xilinx/xilinx/xc7a100t.bin --xdc ../src/arty.xdc --json attosoc.json --write attosoc_routed.json --fasm attosoc.fasm