more linter

tinygrad/codegen/late/regalloc.py

@@ -71,7 +71,7 @@ def alloc(ctx:RegallocContext, cons:tuple[Register, ...], i:int) -> Register:
     offset = ctx.stack_size + (sz - ctx.stack_size % sz) % sz
     ctx.spills[vreg] = UOp.const(dtypes.int32, offset)
     ctx.stack_size = offset + sz
-  return ctx.live.pop(vreg, reg)
+  return ctx.live.pop(vreg) if vreg is not None else reg
 
 def regalloc(ctx:RegallocContext, x:UOp, i:int) -> tuple[UOp, list[UOp]]:
   nsrc, loads = [], []

tinygrad/renderer/isa/isa.py

@@ -40,7 +40,7 @@ def isa_linearize(sink:UOp) -> list[UOp]:
   # this is a toposort with priority
   lst = list(sink.toposort())
   out_degree:defaultdict[UOp, int] = defaultdict(int)
-  priorities:dict[UOp, tuple[int, int, Any]] = {}
+  priorities:dict[UOp, tuple[int, int]] = {}
 
   # get consumers and assign priorities
   # NOTE: this requires the lst be locally toposorted
@@ -129,5 +129,3 @@ class ISARenderer(Renderer):
     if DEBUG >= 7: print_uop_asm(lst)
     if SPEC: type_verify(lst, self.isa_spec)
     return lst
-
-# TODO: shared matchers can go here

tinygrad/renderer/isa/x86.py

@@ -124,7 +124,7 @@ def cmp(x:UOp) -> UOp:
 
 # vshufps xmm2, xmm0, xmm1, imm
 # xmm2 selects its lower 2 32 bits from xmm0 and its upper 2 32 bits from xmm1 according to imm
-def vshufps(x:UOp) -> UOp:
+def vshufps(x:UOp) -> UOp|None:
   def _in(i:int) -> UOp: return s.src[0] if (s:=x.src[i]).op is Ops.GEP else s
   if len(x.src) != 4 or _in(0) is not _in(1) or _in(2) is not _in(3): return None
   return UOp(X86Ops.VSHUFPS, x.dtype, (_in(0), _in(2),
@@ -662,7 +662,7 @@ class X86Renderer(ISARenderer):
   def render(self, uops:list[UOp], lower:bool=True) -> str:
     if lower: uops = self.lower(uops[-1])
     targets: set[UOp] = set()
-    target_loc: list[UOp, int] = []
+    target_loc: list[int] = []
     binary = bytearray()
     for u in uops:
       if u.op in (X86Ops.JL, X86Ops.JB, X86Ops.JE, X86Ops.JNE): targets.add(u.src[0])