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assembly/amd: add pcode ds ops
This commit is contained in:
George Hotz
parent
2bb07d4824
commit
b596f77e33
7 changed files with 4750 additions and 63 deletions
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@ -3,7 +3,7 @@
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from __future__ import annotations
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import ctypes
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from extra.assembly.amd.dsl import Inst, unwrap, FLOAT_ENC, MASK32, MASK64, _f32, _i32, _sext, _f16, _i16, _f64, _i64
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from extra.assembly.amd.pcode import Reg
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from extra.assembly.amd.pcode import Reg, LDSMem
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from extra.assembly.amd.asm import detect_format
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from extra.assembly.amd.autogen.rdna3.gen_pcode import get_compiled_functions
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from extra.assembly.amd.autogen.rdna3.ins import (SOP1, SOP2, SOPC, SOPK, SOPP, SMEM, VOP1, VOP2, VOP3, VOP3SD, VOP3P, VOPC, DS, FLAT, VOPD,
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@ -51,11 +51,6 @@ _D16_LOAD_MAP = {'LOAD_D16_U8': (1,0,0), 'LOAD_D16_I8': (1,1,0), 'LOAD_D16_B16':
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_D16_STORE_MAP = {'STORE_D16_HI_B8': (1,1), 'STORE_D16_HI_B16': (2,1)} # (size, hi)
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FLAT_D16_LOAD = _mem_ops([GLOBALOp, FLATOp], _D16_LOAD_MAP)
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FLAT_D16_STORE = _mem_ops([GLOBALOp, FLATOp], _D16_STORE_MAP)
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DS_LOAD = {DSOp.DS_LOAD_B32: (1,4,0), DSOp.DS_LOAD_B64: (2,4,0), DSOp.DS_LOAD_B128: (4,4,0), DSOp.DS_LOAD_U8: (1,1,0), DSOp.DS_LOAD_I8: (1,1,1), DSOp.DS_LOAD_U16: (1,2,0), DSOp.DS_LOAD_I16: (1,2,1)}
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DS_STORE = {DSOp.DS_STORE_B32: (1,4), DSOp.DS_STORE_B64: (2,4), DSOp.DS_STORE_B128: (4,4), DSOp.DS_STORE_B8: (1,1), DSOp.DS_STORE_B16: (1,2)}
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# 2ADDR ops: load/store two values using offset0 and offset1
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DS_LOAD_2ADDR = {DSOp.DS_LOAD_2ADDR_B32: 4, DSOp.DS_LOAD_2ADDR_B64: 8}
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DS_STORE_2ADDR = {DSOp.DS_STORE_2ADDR_B32: 4, DSOp.DS_STORE_2ADDR_B64: 8}
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SMEM_LOAD = {SMEMOp.S_LOAD_B32: 1, SMEMOp.S_LOAD_B64: 2, SMEMOp.S_LOAD_B128: 4, SMEMOp.S_LOAD_B256: 8, SMEMOp.S_LOAD_B512: 16}
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# VOPD op -> VOP3 op mapping (VOPD is dual-issue of VOP1/VOP2 ops, use VOP3 enums for pseudocode lookup)
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@ -225,31 +220,32 @@ def exec_vector(st: WaveState, inst: Inst, lane: int, lds: bytearray | None = No
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return
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if isinstance(inst, DS):
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op, addr0, vdst = inst.op, (V[inst.addr] + inst.offset0) & 0xffff, inst.vdst
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if op in DS_LOAD:
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cnt, sz, sign = DS_LOAD[op]
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for i in range(cnt): val = int.from_bytes(lds[addr0+i*sz:addr0+i*sz+sz], 'little'); V[vdst + i] = _sext(val, sz * 8) & MASK32 if sign else val
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elif op in DS_STORE:
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cnt, sz = DS_STORE[op]
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for i in range(cnt): lds[addr0+i*sz:addr0+i*sz+sz] = (V[inst.data0 + i] & ((1 << (sz * 8)) - 1)).to_bytes(sz, 'little')
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elif op in DS_LOAD_2ADDR:
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# Load two values from addr+offset0*sz and addr+offset1*sz into vdst (B32: 1 dword each, B64: 2 dwords each)
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# Note: offsets are scaled by data size (4 for B32, 8 for B64) per AMD ISA
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sz = DS_LOAD_2ADDR[op]
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addr0 = (V[inst.addr] + inst.offset0 * sz) & 0xffff
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addr1 = (V[inst.addr] + inst.offset1 * sz) & 0xffff
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cnt = sz // 4 # 1 for B32, 2 for B64
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for i in range(cnt): V[vdst + i] = int.from_bytes(lds[addr0+i*4:addr0+i*4+4], 'little')
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for i in range(cnt): V[vdst + cnt + i] = int.from_bytes(lds[addr1+i*4:addr1+i*4+4], 'little')
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elif op in DS_STORE_2ADDR:
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# Store two values from data0 and data1 to addr+offset0*sz and addr+offset1*sz
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# Note: offsets are scaled by data size (4 for B32, 8 for B64) per AMD ISA
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sz = DS_STORE_2ADDR[op]
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addr0 = (V[inst.addr] + inst.offset0 * sz) & 0xffff
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addr1 = (V[inst.addr] + inst.offset1 * sz) & 0xffff
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cnt = sz // 4
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for i in range(cnt): lds[addr0+i*4:addr0+i*4+4] = (V[inst.data0 + i] & MASK32).to_bytes(4, 'little')
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for i in range(cnt): lds[addr1+i*4:addr1+i*4+4] = (V[inst.data1 + i] & MASK32).to_bytes(4, 'little')
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op, vdst = inst.op, inst.vdst
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if DSOp in compiled and op in compiled[DSOp]:
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fn = compiled[DSOp][op]
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# For B64 operations, DATA/DATA2 access bits [63:32] so we need to pass 64-bit values
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op_name = op.name
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is_b64 = '_B64' in op_name or '_U64' in op_name or '_I64' in op_name or '_F64' in op_name
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is_b128 = '_B128' in op_name
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if is_b128:
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s1 = Reg((V[inst.data0 + 3] << 96) | (V[inst.data0 + 2] << 64) | (V[inst.data0 + 1] << 32) | V[inst.data0])
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s2 = Reg((V[inst.data1 + 3] << 96) | (V[inst.data1 + 2] << 64) | (V[inst.data1 + 1] << 32) | V[inst.data1]) if inst.data1 else Reg(0)
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elif is_b64:
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s1 = Reg((V[inst.data0 + 1] << 32) | V[inst.data0])
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s2 = Reg((V[inst.data1 + 1] << 32) | V[inst.data1]) if inst.data1 else Reg(0)
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else:
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s1, s2 = Reg(V[inst.data0]), Reg(V[inst.data1] if inst.data1 else 0)
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s0, mem = Reg(V[inst.addr]), LDSMem(lds)
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result = fn(s0, s1, s2, Reg(V[vdst]), Reg(st.scc), Reg(st.vcc), lane, Reg(st.exec_mask), st.literal, None,
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offset0=inst.offset0, offset1=inst.offset1, MEM=mem)
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if 'D0' in result: V[vdst] = result['D0']._val & MASK32
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if 'RETURN_DATA' in result:
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# RETURN_DATA can be multi-dword (up to 128 bits for B128 ops)
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val = result['RETURN_DATA']._val
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V[vdst] = val & MASK32
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V[vdst + 1] = (val >> 32) & MASK32
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V[vdst + 2] = (val >> 64) & MASK32
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V[vdst + 3] = (val >> 96) & MASK32
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else: raise NotImplementedError(f"DS op {op}")
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return
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@ -212,7 +212,7 @@ def signext_from_bit(val, bit):
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__all__ = [
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# Classes
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'Reg', 'SliceProxy', 'TypedView',
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'Reg', 'SliceProxy', 'TypedView', 'LDSMem',
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# Pack functions
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'_pack', '_pack32', 'pack', 'pack32',
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# Constants
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@ -341,11 +341,42 @@ class _Denorm:
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f64 = _DenormChecker(64)
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DENORM = _Denorm()
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def _brev(v, bits):
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"""Bit-reverse a value."""
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result = 0
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for i in range(bits): result |= ((v >> i) & 1) << (bits - 1 - i)
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return result
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# ═══════════════════════════════════════════════════════════════════════════════
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# LDS MEMORY ACCESS (for DS instructions)
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# ═══════════════════════════════════════════════════════════════════════════════
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class _LDSAccessor:
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"""Accessor for LDS memory at a specific address. Supports .u32/.f32 etc."""
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__slots__ = ('_lds', '_addr')
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def __init__(self, lds: bytearray, addr: int): self._lds, self._addr = lds, addr & 0xffff
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def _read(self, size: int) -> int:
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return int.from_bytes(self._lds[self._addr:self._addr+size], 'little') if self._addr + size <= len(self._lds) else 0
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def _write(self, size: int, val: int):
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if self._addr + size <= len(self._lds): self._lds[self._addr:self._addr+size] = (int(val) & ((1 << (size*8)) - 1)).to_bytes(size, 'little')
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# Unsigned integer access
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u8 = property(lambda s: s._read(1), lambda s, v: s._write(1, v))
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u16 = property(lambda s: s._read(2), lambda s, v: s._write(2, v))
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u32 = property(lambda s: s._read(4), lambda s, v: s._write(4, v))
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u64 = property(lambda s: s._read(8), lambda s, v: s._write(8, v))
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# Signed integer access
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i8 = property(lambda s: _sext(s._read(1), 8), lambda s, v: s._write(1, v))
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i16 = property(lambda s: _sext(s._read(2), 16), lambda s, v: s._write(2, v))
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i32 = property(lambda s: _sext(s._read(4), 32), lambda s, v: s._write(4, v))
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i64 = property(lambda s: _sext(s._read(8), 64), lambda s, v: s._write(8, v))
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# Float access
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f16 = property(lambda s: _f16(s._read(2)), lambda s, v: s._write(2, v if isinstance(v, int) else _i16(float(v))))
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f32 = property(lambda s: _f32(s._read(4)), lambda s, v: s._write(4, _i32(float(v))))
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f64 = property(lambda s: _f64(s._read(8)), lambda s, v: s._write(8, _i64(float(v))))
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# Bit/byte aliases
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b8, b16, b32, b64 = u8, u16, u32, u64
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class LDSMem:
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"""LDS memory wrapper that supports MEM[addr].u32 style access."""
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__slots__ = ('_lds',)
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def __init__(self, lds: bytearray): self._lds = lds
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def __getitem__(self, addr) -> _LDSAccessor: return _LDSAccessor(self._lds, int(addr))
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class SliceProxy:
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"""Proxy for D0[31:16] that supports .f16/.u16 etc getters and setters."""
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@ -473,10 +504,12 @@ class TypedView:
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@property
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def u32(s): return s if s._bits == 32 and not s._signed else int(s) & MASK32
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MASK128 = (1 << 128) - 1
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class Reg:
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"""GPU register: D0.f32 = S0.f32 + S1.f32 just works."""
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"""GPU register: D0.f32 = S0.f32 + S1.f32 just works. Supports up to 128 bits for DS_LOAD_B128."""
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__slots__ = ('_val',)
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def __init__(self, val=0): self._val = int(val) & MASK64
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def __init__(self, val=0): self._val = int(val) & MASK128
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# Typed views
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u64 = property(lambda s: TypedView(s, 64), lambda s, v: setattr(s, '_val', int(v) & MASK64))
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@ -36,7 +36,7 @@ FIELD_ORDER = {
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SRC_EXTRAS = {233: 'DPP8', 234: 'DPP8FI', 250: 'DPP16', 251: 'VCCZ', 252: 'EXECZ', 254: 'LDS_DIRECT'}
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FLOAT_MAP = {'0.5': 'POS_HALF', '-0.5': 'NEG_HALF', '1.0': 'POS_ONE', '-1.0': 'NEG_ONE', '2.0': 'POS_TWO', '-2.0': 'NEG_TWO',
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'4.0': 'POS_FOUR', '-4.0': 'NEG_FOUR', '1/(2*PI)': 'INV_2PI', '0': 'ZERO'}
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INST_PATTERN = re.compile(r'^([SV]_[A-Z0-9_]+)\s+(\d+)\s*$', re.M)
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INST_PATTERN = re.compile(r'^([SVD]S?_[A-Z0-9_]+)\s+(\d+)\s*$', re.M)
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# Patterns that can't be handled by the DSL (require special handling in emu.py)
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UNSUPPORTED = ['SGPR[', 'V_SWAP', 'eval ', 'FATAL_HALT', 'HW_REGISTERS',
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@ -46,7 +46,7 @@ UNSUPPORTED = ['SGPR[', 'V_SWAP', 'eval ', 'FATAL_HALT', 'HW_REGISTERS',
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'if n.', 'DST.u32', 'addrd = DST', 'addr = DST',
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'BARRIER_STATE', 'ReallocVgprs',
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'GPR_IDX', 'VSKIP', 'specified in', 'TTBL',
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'fp6', 'bf6'] # Malformed pseudocode from PDF
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'fp6', 'bf6', 'GS_REGS', 'M0.base', 'DS_DATA', '= 0..', 'sign(src', 'if no LDS', 'gds_base', 'vector mask'] # Malformed pseudocode from PDF
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# ═══════════════════════════════════════════════════════════════════════════════
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# COMPILER: pseudocode -> Python (minimal transforms)
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@ -68,8 +68,8 @@ def compile_pseudocode(pseudocode: str) -> str:
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lines = []
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indent, need_pass, in_first_match_loop = 0, False, False
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for line in joined_lines:
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line = line.strip()
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if not line or line.startswith('//'): continue
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line = line.split('//')[0].strip() # Strip C-style comments
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if not line: continue
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if line.startswith('if '):
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lines.append(' ' * indent + f"if {_expr(line[3:].rstrip(' then'))}:")
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indent += 1
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@ -351,8 +351,9 @@ def _extract_pseudocode(text: str) -> str | None:
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for line in lines:
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s = line.strip()
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if not s or re.match(r'^\d+ of \d+$', s) or re.match(r'^\d+\.\d+\..*Instructions', s): continue
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if s.startswith(('Notes', 'Functional examples')): break
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if s.startswith(('Notes', 'Functional examples', '•', '-')): break # Stop at notes/bullets
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if s.startswith(('"RDNA', 'AMD ', 'CDNA')): continue
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if '•' in s or '–' in s: continue # Skip lines with bullets/dashes
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if '= lambda(' in s: in_lambda += 1; continue
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if in_lambda > 0:
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if s.endswith(');'): in_lambda -= 1
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@ -362,7 +363,7 @@ def _extract_pseudocode(text: str) -> str | None:
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if s.endswith('.') and not any(p in s for p in ['D0', 'D1', 'S0', 'S1', 'S2', 'SCC', 'VCC', 'tmp', '=']): continue
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if re.match(r'^[a-z].*\.$', s) and '=' not in s: continue
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is_code = (any(p in s for p in ['D0.', 'D1.', 'S0.', 'S1.', 'S2.', 'SCC =', 'SCC ?', 'VCC', 'EXEC', 'tmp =', 'tmp[', 'lane =', 'PC =',
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'D0[', 'D1[', 'S0[', 'S1[', 'S2[']) or
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'D0[', 'D1[', 'S0[', 'S1[', 'S2[', 'MEM[', 'RETURN_DATA']) or
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s.startswith(('if ', 'else', 'elsif', 'endif', 'declare ', 'for ', 'endfor', '//')) or
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re.match(r'^[a-z_]+\s*=', s) or re.match(r'^[a-z_]+\[', s) or (depth > 0 and '=' in s))
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if is_code: result.append(s)
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@ -448,13 +449,13 @@ def _generate_gen_pcode_py(enums, pseudocode, arch) -> str:
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# Get op enums for this arch (import from .ins which re-exports from .enum)
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import importlib
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autogen = importlib.import_module(f"extra.assembly.amd.autogen.{arch}.ins")
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OP_ENUMS = [getattr(autogen, name) for name in ['SOP1Op', 'SOP2Op', 'SOPCOp', 'SOPKOp', 'SOPPOp', 'VOP1Op', 'VOP2Op', 'VOP3Op', 'VOP3SDOp', 'VOP3POp', 'VOPCOp', 'VOP3AOp', 'VOP3BOp'] if hasattr(autogen, name)]
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OP_ENUMS = [getattr(autogen, name) for name in ['SOP1Op', 'SOP2Op', 'SOPCOp', 'SOPKOp', 'SOPPOp', 'VOP1Op', 'VOP2Op', 'VOP3Op', 'VOP3SDOp', 'VOP3POp', 'VOPCOp', 'VOP3AOp', 'VOP3BOp', 'DSOp'] if hasattr(autogen, name)]
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# Build defined ops mapping
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defined_ops: dict[tuple, list] = {}
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for enum_cls in OP_ENUMS:
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for op in enum_cls:
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if op.name.startswith(('S_', 'V_')): defined_ops.setdefault((op.name, op.value), []).append((enum_cls, op))
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if op.name.startswith(('S_', 'V_', 'DS_')): defined_ops.setdefault((op.name, op.value), []).append((enum_cls, op))
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enum_names = [e.__name__ for e in OP_ENUMS]
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lines = [f'''# autogenerated by pdf.py - do not edit
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@ -541,11 +542,16 @@ def _generate_function(cls_name: str, op, pc: str, code: str) -> tuple[str, str]
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is_cmpx = (cls_name in ('VOPCOp', 'VOP3Op')) and 'EXEC.u64[laneId]' in pc
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is_div_scale = 'DIV_SCALE' in op.name
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has_sdst = cls_name == 'VOP3SDOp' and ('VCC.u64[laneId]' in pc or is_div_scale)
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is_ds = cls_name == 'DSOp'
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combined = code + pc
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fn_name = f"_{cls_name}_{op.name}"
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# Function accepts Reg objects directly (uppercase names), laneId is passed directly as int
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lines = [f"def {fn_name}(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None):"]
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# DSOp functions get additional MEM and offset parameters
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if is_ds:
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lines = [f"def {fn_name}(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0):"]
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else:
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lines = [f"def {fn_name}(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None):"]
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# Registers that need special handling (not passed directly)
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# Only init if used but not first assigned as `name = Reg(...)` in the compiled code
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@ -554,6 +560,11 @@ def _generate_function(cls_name: str, op, pc: str, code: str) -> tuple[str, str]
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('SRC0', 'Reg(src0_idx)'), ('VDST', 'Reg(vdst_idx)')]
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if needs_init('tmp'): special_regs.insert(0, ('tmp', 'Reg(0)'))
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if needs_init('saveexec'): special_regs.insert(0, ('saveexec', 'Reg(EXEC._val)'))
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# DS ops: add ADDR, DATA, OFFSET, RETURN_DATA variables
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if is_ds:
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special_regs.extend([('ADDR', 'S0._val'), ('DATA', 'S1'), ('DATA0', 'S1'), ('DATA1', 'S2'), ('DATA2', 'S2'),
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('OFFSET', 'Reg(offset0)'), ('OFFSET0', 'Reg(offset0)'), ('OFFSET1', 'Reg(offset1)'),
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('RETURN_DATA', 'Reg(0)')])
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used = {name for name, _ in special_regs if name in combined}
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# Detect which registers are modified (not just read) - look for assignments
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@ -562,6 +573,8 @@ def _generate_function(cls_name: str, op, pc: str, code: str) -> tuple[str, str]
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modifies_vcc = has_sdst or bool(re.search(r'VCC\.(u32|u64|b32|b64)\s*=|VCC\.u64\[laneId\]\s*=', combined))
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modifies_scc = bool(re.search(r'\bSCC\s*=', combined))
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modifies_pc = bool(re.search(r'\bPC\s*=', combined))
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# DS ops: detect memory writes (MEM[...] = ...)
|
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modifies_mem = is_ds and bool(re.search(r'MEM\[.*\]\.[a-z0-9]+\s*=', combined))
|
||||
|
||||
# Build init code for special registers
|
||||
init_lines = []
|
||||
|
|
@ -587,6 +600,9 @@ def _generate_function(cls_name: str, op, pc: str, code: str) -> tuple[str, str]
|
|||
if modifies_exec: result_items.append("'EXEC': EXEC")
|
||||
if has_d1: result_items.append("'D1': D1")
|
||||
if modifies_pc: result_items.append("'PC': PC")
|
||||
# DS ops: return RETURN_DATA if it was set (matches RETURN_DATA.u32 = or RETURN_DATA[...] =)
|
||||
if is_ds and 'RETURN_DATA' in combined and re.search(r'RETURN_DATA[\.\[].*=', combined):
|
||||
result_items.append("'RETURN_DATA': RETURN_DATA")
|
||||
lines.append(f" return {{{', '.join(result_items)}}}\n")
|
||||
return fn_name, '\n'.join(lines)
|
||||
|
||||
|
|
|
|||
|
|
@ -4256,3 +4256,217 @@ class TestDS2Addr(unittest.TestCase):
|
|||
# v6,v7 from addr 8-15: 0x33333333, 0x44444444
|
||||
self.assertEqual(st.vgpr[0][6], 0x33333333, "v6 should be 0x33333333")
|
||||
self.assertEqual(st.vgpr[0][7], 0x44444444, "v7 should be 0x44444444")
|
||||
|
||||
|
||||
class TestDSAtomic(unittest.TestCase):
|
||||
"""Tests for DS atomic instructions (add, max, min, and, or, xor, cmpstore, etc.)."""
|
||||
|
||||
def test_ds_max_rtn_u32(self):
|
||||
"""DS_MAX_RTN_U32: atomically store max(mem, data) and return old value."""
|
||||
instructions = [
|
||||
v_mov_b32_e32(v[10], 0), # addr = 0
|
||||
s_mov_b32(s[2], 100),
|
||||
v_mov_b32_e32(v[0], s[2]), # initial value = 100
|
||||
ds_store_b32(addr=v[10], data0=v[0], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
s_mov_b32(s[2], 200),
|
||||
v_mov_b32_e32(v[1], s[2]), # data = 200 (greater than 100)
|
||||
ds_max_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
ds_load_b32(addr=v[10], vdst=v[3], offset0=0), # read result
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
]
|
||||
st = run_program(instructions, n_lanes=1)
|
||||
self.assertEqual(st.vgpr[0][2], 100, "v2 should have old value (100)")
|
||||
self.assertEqual(st.vgpr[0][3], 200, "v3 should have max(100, 200) = 200")
|
||||
|
||||
def test_ds_max_u32_no_rtn(self):
|
||||
"""DS_MAX_U32 (no RTN): atomically store max, no return value."""
|
||||
instructions = [
|
||||
v_mov_b32_e32(v[10], 0),
|
||||
s_mov_b32(s[2], 100),
|
||||
v_mov_b32_e32(v[0], s[2]), # initial = 100
|
||||
ds_store_b32(addr=v[10], data0=v[0], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
s_mov_b32(s[2], 200),
|
||||
v_mov_b32_e32(v[1], s[2]), # data = 200
|
||||
ds_max_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
]
|
||||
st = run_program(instructions, n_lanes=1)
|
||||
self.assertEqual(st.vgpr[0][3], 200, "v3 should have max(100, 200) = 200")
|
||||
|
||||
def test_ds_min_rtn_u32(self):
|
||||
"""DS_MIN_RTN_U32: atomically store min(mem, data) and return old value."""
|
||||
instructions = [
|
||||
v_mov_b32_e32(v[10], 0),
|
||||
s_mov_b32(s[2], 200),
|
||||
v_mov_b32_e32(v[0], s[2]), # initial = 200
|
||||
ds_store_b32(addr=v[10], data0=v[0], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
s_mov_b32(s[2], 100),
|
||||
v_mov_b32_e32(v[1], s[2]), # data = 100
|
||||
ds_min_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
]
|
||||
st = run_program(instructions, n_lanes=1)
|
||||
self.assertEqual(st.vgpr[0][2], 200, "v2 should have old value (200)")
|
||||
self.assertEqual(st.vgpr[0][3], 100, "v3 should have min(200, 100) = 100")
|
||||
|
||||
def test_ds_and_rtn_b32(self):
|
||||
"""DS_AND_RTN_B32: atomically AND mem with data and return old value."""
|
||||
instructions = [
|
||||
v_mov_b32_e32(v[10], 0),
|
||||
s_mov_b32(s[2], 0xFF00FF00),
|
||||
v_mov_b32_e32(v[0], s[2]), # initial = 0xFF00FF00
|
||||
ds_store_b32(addr=v[10], data0=v[0], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
s_mov_b32(s[2], 0xFFFF0000),
|
||||
v_mov_b32_e32(v[1], s[2]), # data = 0xFFFF0000
|
||||
ds_and_rtn_b32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
]
|
||||
st = run_program(instructions, n_lanes=1)
|
||||
self.assertEqual(st.vgpr[0][2], 0xFF00FF00, "v2 should have old value")
|
||||
self.assertEqual(st.vgpr[0][3], 0xFF000000, "v3 should have 0xFF00FF00 & 0xFFFF0000 = 0xFF000000")
|
||||
|
||||
def test_ds_or_rtn_b32(self):
|
||||
"""DS_OR_RTN_B32: atomically OR mem with data and return old value."""
|
||||
instructions = [
|
||||
v_mov_b32_e32(v[10], 0),
|
||||
s_mov_b32(s[2], 0x00FF0000),
|
||||
v_mov_b32_e32(v[0], s[2]), # initial = 0x00FF0000
|
||||
ds_store_b32(addr=v[10], data0=v[0], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
s_mov_b32(s[2], 0x000000FF),
|
||||
v_mov_b32_e32(v[1], s[2]), # data = 0x000000FF
|
||||
ds_or_rtn_b32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
]
|
||||
st = run_program(instructions, n_lanes=1)
|
||||
self.assertEqual(st.vgpr[0][2], 0x00FF0000, "v2 should have old value")
|
||||
self.assertEqual(st.vgpr[0][3], 0x00FF00FF, "v3 should have 0x00FF0000 | 0x000000FF = 0x00FF00FF")
|
||||
|
||||
def test_ds_xor_rtn_b32(self):
|
||||
"""DS_XOR_RTN_B32: atomically XOR mem with data and return old value."""
|
||||
instructions = [
|
||||
v_mov_b32_e32(v[10], 0),
|
||||
s_mov_b32(s[2], 0xAAAAAAAA),
|
||||
v_mov_b32_e32(v[0], s[2]), # initial = 0xAAAAAAAA
|
||||
ds_store_b32(addr=v[10], data0=v[0], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
s_mov_b32(s[2], 0xFFFFFFFF),
|
||||
v_mov_b32_e32(v[1], s[2]), # data = 0xFFFFFFFF
|
||||
ds_xor_rtn_b32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
]
|
||||
st = run_program(instructions, n_lanes=1)
|
||||
self.assertEqual(st.vgpr[0][2], 0xAAAAAAAA, "v2 should have old value")
|
||||
self.assertEqual(st.vgpr[0][3], 0x55555555, "v3 should have 0xAAAAAAAA ^ 0xFFFFFFFF = 0x55555555")
|
||||
|
||||
def test_ds_cmpstore_b32_match(self):
|
||||
"""DS_CMPSTORE_B32: conditional store when compare matches."""
|
||||
instructions = [
|
||||
v_mov_b32_e32(v[10], 0),
|
||||
s_mov_b32(s[2], 100),
|
||||
v_mov_b32_e32(v[0], s[2]), # initial = 100
|
||||
ds_store_b32(addr=v[10], data0=v[0], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
s_mov_b32(s[2], 200),
|
||||
v_mov_b32_e32(v[1], s[2]), # new value = 200
|
||||
s_mov_b32(s[2], 100),
|
||||
v_mov_b32_e32(v[2], s[2]), # compare = 100 (matches current)
|
||||
ds_cmpstore_b32(addr=v[10], data0=v[1], data1=v[2], vdst=v[3], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
ds_load_b32(addr=v[10], vdst=v[4], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
]
|
||||
st = run_program(instructions, n_lanes=1)
|
||||
self.assertEqual(st.vgpr[0][4], 200, "mem should be updated to 200 (compare matched)")
|
||||
|
||||
def test_ds_cmpstore_b32_no_match(self):
|
||||
"""DS_CMPSTORE_B32: no store when compare doesn't match."""
|
||||
instructions = [
|
||||
v_mov_b32_e32(v[10], 0),
|
||||
s_mov_b32(s[2], 100),
|
||||
v_mov_b32_e32(v[0], s[2]), # initial = 100
|
||||
ds_store_b32(addr=v[10], data0=v[0], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
s_mov_b32(s[2], 200),
|
||||
v_mov_b32_e32(v[1], s[2]), # new value = 200
|
||||
s_mov_b32(s[2], 50),
|
||||
v_mov_b32_e32(v[2], s[2]), # compare = 50 (doesn't match 100)
|
||||
ds_cmpstore_b32(addr=v[10], data0=v[1], data1=v[2], vdst=v[3], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
ds_load_b32(addr=v[10], vdst=v[4], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
]
|
||||
st = run_program(instructions, n_lanes=1)
|
||||
self.assertEqual(st.vgpr[0][4], 100, "mem should still be 100 (compare didn't match)")
|
||||
|
||||
def test_ds_inc_u32(self):
|
||||
"""DS_INC_U32: increment with wrap."""
|
||||
instructions = [
|
||||
v_mov_b32_e32(v[10], 0),
|
||||
s_mov_b32(s[2], 5),
|
||||
v_mov_b32_e32(v[0], s[2]), # initial = 5
|
||||
ds_store_b32(addr=v[10], data0=v[0], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
s_mov_b32(s[2], 10),
|
||||
v_mov_b32_e32(v[1], s[2]), # limit = 10
|
||||
ds_inc_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
]
|
||||
st = run_program(instructions, n_lanes=1)
|
||||
self.assertEqual(st.vgpr[0][2], 5, "v2 should have old value (5)")
|
||||
self.assertEqual(st.vgpr[0][3], 6, "v3 should have incremented value (6)")
|
||||
|
||||
def test_ds_dec_u32(self):
|
||||
"""DS_DEC_U32: decrement with wrap."""
|
||||
instructions = [
|
||||
v_mov_b32_e32(v[10], 0),
|
||||
s_mov_b32(s[2], 5),
|
||||
v_mov_b32_e32(v[0], s[2]), # initial = 5
|
||||
ds_store_b32(addr=v[10], data0=v[0], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
s_mov_b32(s[2], 10),
|
||||
v_mov_b32_e32(v[1], s[2]), # limit = 10
|
||||
ds_dec_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
]
|
||||
st = run_program(instructions, n_lanes=1)
|
||||
self.assertEqual(st.vgpr[0][2], 5, "v2 should have old value (5)")
|
||||
self.assertEqual(st.vgpr[0][3], 4, "v3 should have decremented value (4)")
|
||||
|
||||
def test_ds_dec_u32_wrap(self):
|
||||
"""DS_DEC_U32: wraps to limit when value is 0 or > limit."""
|
||||
instructions = [
|
||||
v_mov_b32_e32(v[10], 0),
|
||||
s_mov_b32(s[2], 0),
|
||||
v_mov_b32_e32(v[0], s[2]), # initial = 0
|
||||
ds_store_b32(addr=v[10], data0=v[0], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
s_mov_b32(s[2], 10),
|
||||
v_mov_b32_e32(v[1], s[2]), # limit = 10
|
||||
ds_dec_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
|
||||
s_waitcnt(lgkmcnt=0),
|
||||
]
|
||||
st = run_program(instructions, n_lanes=1)
|
||||
self.assertEqual(st.vgpr[0][2], 0, "v2 should have old value (0)")
|
||||
self.assertEqual(st.vgpr[0][3], 10, "v3 should wrap to limit (10)")
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue