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fix(egpu): program BAR addresses for Thunderbolt eGPUs on Apple Silicon
On macOS Apple Silicon, Thunderbolt-connected eGPUs don't get BAR addresses assigned by the OS. The BAR registers in PCI config space remain 0x00000000, causing _CopyDeviceMemoryWithIndex to return mappings that read as 0xFFFFFFFF (unmapped memory), making the GPU unusable for compute. This patch adds ProgramBARAddresses() to TinyGPUDriver::Start_Impl, which: 1. Checks if BAR0 is unassigned (0x00000000 or 0xFFFFFFFF) 2. Determines each BAR's size requirement by writing/reading 0xFFFFFFFF 3. Reads the parent Thunderbolt bridge's memory aperture (MEM base/limit, prefetchable MEM base/limit) from PCI config space 4. Allocates naturally-aligned BAR addresses from the bridge aperture 5. Writes the addresses to BAR registers in config space 6. Re-enables Memory Space and Bus Master in the command register 7. Logs all steps for debugging This mirrors what Linux does in pci_assign_resource() and what mac-amdgpu does manually for the R9700. Without this, the DriverKit extension can enumerate the GPU but cannot access its MMIO registers. Tested-on: AMD Radeon AI PRO R9700 32GB (RDNA4) on M4 Mac Mini via ACASIS G4Pro Thunderbolt 4 enclosure. Fixes: #15813, #15864, #16714 Related: #15730, #15744
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2 changed files with 214 additions and 2 deletions
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@ -31,6 +31,209 @@ void TinyGPUDriver::free()
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super::free();
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}
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void TinyGPUDriver::ProgramBARAddresses()
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{
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// On Apple Silicon, macOS may not assign BAR addresses for Thunderbolt eGPUs.
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// The BAR registers in PCI config space remain 0x00000000, causing
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// _CopyDeviceMemoryWithIndex to return mappings that read as 0xFFFFFFFF.
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//
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// This function checks if BARs are unassigned and programs them by:
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// 1. Determining each BAR's size requirement (write 0xFFFFFFFF, read back)
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// 2. Reading the parent Thunderbolt bridge's memory aperture
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// 3. Allocating BAR addresses from the aperture
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// 4. Writing the addresses to BAR registers
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// 5. Re-enabling Memory Space
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os_log(OS_LOG_DEFAULT, "tinygpu: checking BAR assignments");
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// Check if BAR0 is already assigned by the OS
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uint32_t bar0 = 0;
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ivars->pci->ConfigurationRead32(kIOPCIConfigurationOffsetBaseAddress0, &bar0);
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if (bar0 != 0 && bar0 != 0xFFFFFFFF) {
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os_log(OS_LOG_DEFAULT, "tinygpu: BAR0 already assigned (0x%08x), skipping BAR programming", bar0);
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return;
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}
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os_log(OS_LOG_DEFAULT, "tinygpu: BAR0 unassigned (0x%08x), programming BAR addresses for eGPU", bar0);
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// Disable memory and I/O access while programming BARs
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uint16_t cmd = 0;
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ivars->pci->ConfigurationRead16(kIOPCIConfigurationOffsetCommand, &cmd);
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ivars->pci->ConfigurationWrite16(kIOPCIConfigurationOffsetCommand, cmd & ~(kIOPCICommandIOSpace | kIOPCICommandMemorySpace));
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// Step 1: Determine BAR sizes
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uint64_t bar_sizes[6] = {};
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bool bar_64bit[6] = {};
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uint32_t bar_origins[6] = {};
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for (int i = 0; i < 6; ) {
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uint32_t offset = kIOPCIConfigurationOffsetBaseAddress0 + i * 4;
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// Save original
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ivars->pci->ConfigurationRead32(offset, &bar_origins[i]);
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// Write all 1s to determine size
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ivars->pci->ConfigurationWrite32(offset, 0xFFFFFFFF);
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uint32_t readback = 0;
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ivars->pci->ConfigurationRead32(offset, &readback);
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// Restore original
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ivars->pci->ConfigurationWrite32(offset, bar_origins[i]);
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if (readback == 0 || readback == 0xFFFFFFFF) {
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bar_sizes[i] = 0;
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bar_64bit[i] = false;
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i++;
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continue;
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}
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// Decode BAR type
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uint8_t bar_type = readback & 0x7;
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bar_64bit[i] = (bar_type == 0x4);
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// Compute size: mask off type/info bits, invert, add 1
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uint32_t mask = readback & ~0xF;
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uint64_t size = ~(uint64_t)mask + 1;
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if (bar_64bit[i] && i + 1 < 6) {
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// For 64-bit BARs, also probe upper 32 bits
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uint32_t offset_hi = kIOPCIConfigurationOffsetBaseAddress0 + (i + 1) * 4;
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uint32_t orig_hi = 0;
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ivars->pci->ConfigurationRead32(offset_hi, &orig_hi);
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ivars->pci->ConfigurationWrite32(offset_hi, 0xFFFFFFFF);
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uint32_t readback_hi = 0;
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ivars->pci->ConfigurationRead32(offset_hi, &readback_hi);
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ivars->pci->ConfigurationWrite32(offset_hi, orig_hi);
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bar_origins[i + 1] = orig_hi;
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// 64-bit size = lower 32 inverted + upper 32 inverted << 32
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uint64_t size_hi = (~(uint64_t)readback_hi) << 32;
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bar_sizes[i] = (size & 0xFFFFFFFF) | size_hi;
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if (bar_sizes[i] == 0) bar_sizes[i] = ((uint64_t)1 << 32);
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bar_sizes[i + 1] = 0; // Upper half is part of the same BAR
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os_log(OS_LOG_DEFAULT, "tinygpu: BAR%d: size=0x%llx 64bit=1", i, bar_sizes[i]);
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i += 2;
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} else {
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bar_sizes[i] = size;
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os_log(OS_LOG_DEFAULT, "tinygpu: BAR%d: size=0x%llx 64bit=0", i, size);
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i++;
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}
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}
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// Step 2: Read parent bridge memory aperture
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// Thunderbolt bridges expose memory windows at standard PCI bridge config offsets
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// Offset 0x20: Memory Base (16-bit, lower 28 bits of base address, 1MB aligned)
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// Offset 0x22: Memory Limit (16-bit, lower 28 bits of limit address)
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// Offset 0x24: Prefetchable Memory Base Lower (16-bit)
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// Offset 0x28: Prefetchable Memory Base Upper (32-bit)
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// Offset 0x2C: Prefetchable Memory Limit Upper (32-bit)
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OSObject* parentObj = nullptr;
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ivars->pci->CopyParent(&parentObj);
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IOPCIDevice* bridge = OSDynamicCast(IOPCIDevice, parentObj);
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uint64_t mem_base = 0, mem_limit = 0;
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if (bridge) {
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bridge->Open(this, 0);
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uint16_t mem_base_reg = 0, mem_limit_reg = 0;
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bridge->ConfigurationRead16(0x20, &mem_base_reg);
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bridge->ConfigurationRead16(0x22, &mem_limit_reg);
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// Decode: Memory Base/Limit are in units of 1MB, aligned to 1MB boundaries
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mem_base = ((uint64_t)(mem_base_reg & 0xFFF0) << 16);
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mem_limit = (((uint64_t)(mem_limit_reg & 0xFFF0) << 16) | 0xFFFFF);
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os_log(OS_LOG_DEFAULT, "tinygpu: bridge mem window 0x%llx - 0x%llx (base_reg=0x%04x limit_reg=0x%04x)", mem_base, mem_limit, mem_base_reg, mem_limit_reg);
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// Also check prefetchable memory window for 64-bit BARs
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uint16_t pref_base_low = 0, pref_limit_low = 0;
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uint32_t pref_base_hi = 0, pref_limit_hi = 0;
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bridge->ConfigurationRead16(0x24, &pref_base_low);
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bridge->ConfigurationRead16(0x26, &pref_limit_low);
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bridge->ConfigurationRead32(0x28, &pref_base_hi);
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bridge->ConfigurationRead32(0x2C, &pref_limit_hi);
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uint64_t pref_base = ((uint64_t)(pref_base_low & 0xFFF0) << 16) | ((uint64_t)pref_base_hi << 32);
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uint64_t pref_limit = (((uint64_t)(pref_limit_low & 0xFFF0) << 16) | 0xFFFFF) | ((uint64_t)pref_limit_hi << 32);
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os_log(OS_LOG_DEFAULT, "tinygpu: bridge pref mem window 0x%llx - 0x%llx", pref_base, pref_limit);
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// Use prefetchable window for 64-bit BARs if available
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if (pref_base != 0 && pref_limit > pref_base) {
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// Use non-prefetchable for 32-bit BARs, prefetchable for 64-bit BARs
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// For now, we allocate everything from the larger window
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if (pref_limit - pref_base > mem_limit - mem_base) {
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mem_base = pref_base;
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mem_limit = pref_limit;
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os_log(OS_LOG_DEFAULT, "tinygpu: using pref mem window for BAR allocation (larger)");
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}
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}
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bridge->Close(this, 0);
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} else {
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os_log(OS_LOG_DEFAULT, "tinygpu: WARNING: parent is not IOPCIDevice, cannot determine bridge aperture");
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}
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if (parentObj) parentObj->release();
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// Step 3: Allocate and program BAR addresses
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if (mem_base == 0 && mem_limit == 0) {
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os_log(OS_LOG_DEFAULT, "tinygpu: WARNING: bridge memory window not available, cannot program BARs");
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ivars->pci->ConfigurationWrite16(kIOPCIConfigurationOffsetCommand, cmd);
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return;
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}
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uint64_t next_addr = mem_base;
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for (int i = 0; i < 6; ) {
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if (bar_sizes[i] == 0) { i++; continue; }
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// Align to BAR size (PCI BARs must be naturally aligned)
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uint64_t alignment = bar_sizes[i];
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uint64_t addr = (next_addr + alignment - 1) & ~(alignment - 1);
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if (addr + bar_sizes[i] > mem_limit) {
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os_log(OS_LOG_DEFAULT, "tinygpu: ERROR: not enough space for BAR%d (need 0x%llx at 0x%llx, limit 0x%llx)", i, bar_sizes[i], addr, mem_limit);
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break;
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}
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uint32_t offset = kIOPCIConfigurationOffsetBaseAddress0 + i * 4;
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if (bar_64bit[i]) {
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uint32_t bar_lo = (uint32_t)(addr & ~0xF) | 0x04; // 64-bit, prefetchable bit preserved
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uint32_t bar_hi = (uint32_t)(addr >> 32);
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ivars->pci->ConfigurationWrite32(offset, bar_lo);
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ivars->pci->ConfigurationWrite32(offset + 4, bar_hi);
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os_log(OS_LOG_DEFAULT, "tinygpu: BAR%d (64-bit): addr=0x%llx size=0x%llx lo=0x%08x hi=0x%08x", i, addr, bar_sizes[i], bar_lo, bar_hi);
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next_addr = addr + bar_sizes[i];
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i += 2;
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} else {
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uint32_t bar_val = (uint32_t)(addr & ~0xF) | 0x00; // 32-bit, non-prefetchable
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ivars->pci->ConfigurationWrite32(offset, bar_val);
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os_log(OS_LOG_DEFAULT, "tinygpu: BAR%d (32-bit): addr=0x%llx size=0x%llx val=0x%08x", i, addr, bar_sizes[i], bar_val);
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next_addr = addr + bar_sizes[i];
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i++;
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}
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}
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// Step 4: Re-enable Memory Space and Bus Master
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ivars->pci->ConfigurationWrite16(kIOPCIConfigurationOffsetCommand, cmd);
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// Verify BAR programming
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os_log(OS_LOG_DEFAULT, "tinygpu: BAR verification:");
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for (int i = 0; i < 6; i++) {
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uint32_t offset = kIOPCIConfigurationOffsetBaseAddress0 + i * 4;
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uint32_t val = 0;
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ivars->pci->ConfigurationRead32(offset, &val);
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if (val != 0) {
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os_log(OS_LOG_DEFAULT, "tinygpu: BAR%d = 0x%08x", i, val);
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}
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}
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os_log(OS_LOG_DEFAULT, "tinygpu: BAR address programming complete");
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}
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kern_return_t TinyGPUDriver::Start_Impl(IOService* in_provider)
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{
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IOServiceName service_name;
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@ -59,6 +262,11 @@ kern_return_t TinyGPUDriver::Start_Impl(IOService* in_provider)
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commandRegister |= (kIOPCICommandIOSpace | kIOPCICommandBusMaster | kIOPCICommandMemorySpace);
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ivars->pci->ConfigurationWrite16(kIOPCIConfigurationOffsetCommand, commandRegister);
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// Program BAR addresses for eGPUs where macOS doesn't assign them.
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// On Apple Silicon Thunderbolt, BAR registers may remain 0x00000000,
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// causing _CopyDeviceMemoryWithIndex to fail silently.
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ProgramBARAddresses();
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memcpy((void*)service_name, (void*)"tinygpu\0", 8);
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SetName(service_name);
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@ -195,4 +403,4 @@ kern_return_t TinyGPUDriver::ResetDevice()
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IOPCIDevice* TinyGPUDriver::GetPCI()
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{
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return ivars->pci;
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}
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}
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@ -35,6 +35,10 @@ public:
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kern_return_t CfgWrite(uint32_t off, uint32_t size, uint32_t val) LOCALONLY;
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kern_return_t ResetDevice() LOCALONLY;
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IOPCIDevice* GetPCI() LOCALONLY;
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// Program BAR addresses for eGPUs where macOS doesn't assign them.
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// Called from Start_Impl after enabling Memory Space and Bus Master.
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void ProgramBARAddresses() LOCALONLY;
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};
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#endif /* TinyGPUDriver_h */
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#endif /* TinyGPUDriver_h */
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