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Author	SHA1	Message	Date
Christopher Milan	0de519c7c2	[pr] fewer simplify calls in image_fixup (#15283)	2026-03-16 06:57:52 -04:00
nimlgen	27e29127b5	system: remote prereqs (#15290) ... * x * new format for apl * this * typing * rpc * tuple * linter+new tinygpu	2026-03-16 18:45:41 +08:00
chenyu	837b06c609	style cleanups in allocations.py [pr] (#15295)	2026-03-16 05:45:24 -04:00
George Hotz	476276f4b4	support grads on tuples (#15287) ... * support grads on tuples * simpler * grad_fxn works * cleanups * unused	2026-03-16 17:39:34 +08:00
chenyu	20799df10b	remove Ops.ASSIGN [pr] (#15294) ... goodbye	2026-03-16 05:22:21 -04:00
chenyu	b3378e7022	UOp.assign is store+after [pr] (#15292)	2026-03-16 04:51:50 -04:00
George Hotz	2e1c81c23f	allow_implicit to disable implicit params (#15291) ... * allow_implicit to disable implicit params * get both Tensor and UOp * no implicits in llm	2026-03-16 16:40:14 +08:00
chenyu	a0d1444790	Tensor.assign is store+after [pr] (#15288) ... * Tensor.assign is store+after [pr] * put that back	2026-03-16 04:04:55 -04:00
George Hotz	08662bc4ab	add TUPLE/GETTUPLE, simple tests pass (#15286) ... * simple tuple stuff passes * resolved	2026-03-16 15:06:02 +08:00
nimlgen	e7705fe311	system: pcidev doesn't care about bars (#15284)	2026-03-16 14:45:43 +08:00
nimlgen	ff0bcc8de0	system: iface p1 changes (#15278)	2026-03-16 10:48:25 +08:00
qazal	4445f50356	viz: variable duration rdna barriers (#15277) ... * viz: variable length rdna barriers * work * tiny changes * simple wave simd test * small wave sync test * good multi barrier bug find * simple fix * wave_sync asserts * rdna4 work * more rdna4 * find more bugs in my model * it's so much simpler * wave_sync tests duration * r4 * should just call this rdna4	2026-03-16 06:06:19 +09:00
qazal	5cd1daa3bc	cdna asm_gemm in one file, remove old rdna3 asm (#15281)	2026-03-16 04:32:30 +09:00
chenyu	cd14e8e64b	allocations contiguous is store+after (#15280)	2026-03-15 11:58:40 -04:00
qazal	7b6211fdd7	sqtt: remove discover_ops script (#15279)	2026-03-15 22:17:06 +09:00
wozeparrot	473e5e4368	feat: make USE_ATOMICS embedding bwd faster (#15151)	2026-03-14 21:21:10 -07:00
qazal	3858bfc83d	sqtt: CDNA inst decodes (#15274) ... * sqtt: CDNA inst decodes * JUMP packets other way * cdna insts * r3 * r4 * lds from simd1 and simd2	2026-03-14 21:03:46 +09:00
Christopher Milan	d753c5d7e5	IMAGE=1 image_conv2d pads for bank conflicts (#15252)	2026-03-14 07:59:16 -04:00
Christopher Milan	9047249a7c	m.where(x.pad_to(m.shape), Invalid) ranges shrink (#15275)	2026-03-14 07:26:36 -04:00
nimlgen	f392c53c66	system: merge remote into pciiface (#15273) ... * system: merge remote into pciiface * clenaer * move * mypy * fix	2026-03-14 18:44:20 +08:00
chenyu	13eec8fbe8	remove unused assign rules [pr] (#15268)	2026-03-14 05:37:49 -04:00
Christopher Milan	dabdc986df	shrink guarded ranges, try 2 (#15272)	2026-03-14 04:24:05 -04:00
Christopher Milan	7cf4b16c91	Revert "shrink guarded ranges" (#15271)	2026-03-14 03:44:38 -04:00
Christopher Milan	d9951e2f8e	shrink guarded ranges (#15263)	2026-03-14 03:38:48 -04:00
qazal	43ffd66fda	viz: oneline inst list (#15269) ... * viz: oneline inst list * save 5 chars * gradual padding	2026-03-14 15:37:18 +09:00
George Hotz	86f17468ed	store in spec + USB BOT fix (#15265) ... * move spec to store * usb bot flag * Revert "usb bot flag" This reverts commit 7b8b7824f0. * fix assert	2026-03-14 13:25:05 +08:00
George Hotz	06d7cddb33	amd_copy_matmul is cleaner (#15248) ... * amd_copy_matmul is cleaner * it runs * replicated stuff * add tid there * it runs * cleanup * x.src[1] * flatten * move that * keep that assert	2026-03-14 12:56:09 +08:00
chenyu	b3600e4774	don't emit assign in transform_precompiled_call [pr] (#15262)	2026-03-13 22:42:35 -04:00
qazal	4d60312f7f	viz: asm python dsl syntax highlighting (#15259)	2026-03-14 06:37:43 +09:00
qazal	6209ddfc90	viz: improve disasm of s_code_end (#15258) ... * viz: improve amd disasm of s_code_end * better tests * order was good	2026-03-14 03:31:14 +09:00
wozeparrot	a191ac0566	llama: use mlperf model (#15257)	2026-03-13 08:08:32 -07:00
Sieds Lykles	4b59083d7c	assign into empty works (#15256)	2026-03-13 10:24:29 -04:00
qazal	60b1b908c6	sqtt: CDNA layout header packet is the same size (#15255)	2026-03-13 22:28:24 +09:00
nimlgen	4e21735f31	system: update tinygpu app (#15247)	2026-03-13 20:36:57 +08:00
nimlgen	1fbe1fef2c	move write_configs to drivers (#15253)	2026-03-13 19:02:34 +08:00
chenyu	018c01508d	test case for call precompile multi (#15254)	2026-03-13 06:28:43 -04:00
nimlgen	bc16f80b50	am: remove dma_regions param (#15251) ... * am: remove dma_regions param * linter	2026-03-13 18:12:48 +08:00
chenyu	576e7f985f	remove handle_assign_mops [pr] (#15249)	2026-03-13 01:53:21 -04:00
Christopher Milan	c251fc67c5	ci: consider arch in venv and apt caches and go back to 3.12 (#15250)	2026-03-13 00:36:49 -04:00
Christopher Milan	d4b947ea9a	ci: explicitly request python 3.12.10 instead of 3.12 (#15246) ... 3.12.10 is the most recent 3.12 version that has toolcache builds for linux, macos, and windows	2026-03-12 23:00:46 -04:00
George Hotz	a7d2429c21	amd_uop_matmul more cleanups (#15240)	2026-03-13 10:24:43 +08:00
qazal	d893b14193	sqtt: update cdna packet names (#15243) ... * sqtt: update cdna packet names * change * order	2026-03-13 08:49:09 +09:00
wozeparrot	749162bd2f	llama memory tweaks (#15223)	2026-03-12 12:36:23 -07:00
qazal	9a7173b7a0	viz: visualize full range of shader clock frequency, auto zoom to kernel range (#15225) ... * start this * work * rm those * relative to start cycle * cleanup * cover the full range of packets * correct event type * start the ui change * fit=true * better * always the zoom identity * diff cleanup * shader engine itrace can be turned off	2026-03-13 00:07:31 +09:00
chenyu	d9c09397c0	Ops.STORE is shapeless [pr] (#15239)	2026-03-12 09:05:30 -04:00
nimlgen	d746ccb791	system: fix vfio (#15235)	2026-03-12 18:31:00 +08:00
nimlgen	d104a903f8	system: print output when err (#15230)	2026-03-12 18:30:49 +08:00
George Hotz	e560a46f59	update amd_uop_matmul (#15236) ... * update amd_uop_matmul * use custom kernel * simpler * ignore	2026-03-12 17:33:12 +08:00
chenyu	90b7f4341d	failed two level divmod recombine case (#15233)	2026-03-12 04:04:36 -04:00
chenyu	8b8d9a443c	remove unused invalid rules [pr] (#15231)	2026-03-12 03:10:34 -04:00