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Author SHA1 Message Date
qazal
dddd0e384f
 		ALLOW_DEVICE_USAGE=0 in codegen (#14238) 2026-01-20 15:15:16 +09:00
George Hotz
0243f4a0f1
 		clear wins from ucode branch (#14243) 
* clear wins from ucode branch

* two more

* revert those
 2026-01-20 15:11:09 +09:00
George Hotz
5e24643889
 		minor import speedups (#14244) 
* minor import speedups

* server stuff in server places

* pre-commit

* fix
 2026-01-20 15:05:36 +09:00
George Hotz
d60a155e48
 		defer compilation of upats (#14242) 
* defer compilation of upats

* mypy
 2026-01-20 13:50:00 +09:00
George Hotz
56c8926d32
 		import speedups: refactor validate to late import (#14241) 
* refactor validate to late import

* preommit stuff

* fix mypy
 2026-01-20 13:23:39 +09:00
chenyu
9d3b1cf1e7
 		simpler _cached_to_python_const (#14236) 2026-01-19 23:10:53 -05:00
qazal
b1c5a242b7
 		Revert "move is_dtype_supported logic to renderer (#14188)" (#14237) 
This reverts commit 161fee9a48.
 2026-01-20 12:19:14 +09:00
wozeparrot
1f89eaf790
 		tk: fa bert mask fix + some numerical stability improvements (#14214) 2026-01-19 19:18:07 -08:00
chenyu
9ea63d7d52
 		failed test case for onnx IF with jit (#14235) 
silently fails now since onnx treats IF cond as a const
 2026-01-19 18:10:05 -05:00
Garret Castro
b65dc9fd8e
 		refactor: use generic type for ContextVar [pr] (#13998) 
* use generic type for context var

removes ops_python string cast thing, allows for handling of other string vars like `_CC`

* update Context.old_context type

---------

Co-authored-by: chenyu <chenyu@fastmail.com>
 2026-01-19 13:37:54 -05:00
Martin Szewieczek
7010c176cf
 		pre commit: fix path to test_assign.py (#14231) 2026-01-19 13:36:30 -05:00
Christopher Milan
34f6192739
 		look for cuda in /opt/cuda (#14230) 
* look for cuda in /opt/cuda

* regen
 2026-01-19 11:51:00 -05:00
qazal
0f61cbd51f
 		viz: draw shapes directly on the canvas (#14229) 2026-01-20 00:57:06 +09:00
nimlgen
acb0045ba0
 		system: alloc_sysmem is part of interface (#14226) 2026-01-19 18:15:54 +03:00
qazal
ab426cb671
 		viz: simplify row line logic (#14227) 2026-01-20 00:00:28 +09:00
nimlgen
01653db4fd
 		nv: GPPut is mmiointerface (#14225) 2026-01-19 17:36:26 +03:00
nimlgen
7cb7abeeb0
 		amd: fix scratch_wave64_lane_byte_size (#14223) 2026-01-19 15:21:39 +03:00
nimlgen
979ce211f7
 		amd: missing self in aql's exec (#14224) 2026-01-19 14:27:54 +03:00
George Hotz
31bcbed6bb
 		AMD_DISABLE_SDMA for testing with -n12 (#14216) 2026-01-19 16:10:30 +09:00
qazal
578a4a50d3
 		viz: row lines in timeline (#14213) 
* simple start, already works for memory graph

* add height to exec packets

* math.max, border-color

* borderline is in pixels

* row border color
 2026-01-19 13:01:43 +09:00
Christopher Milan
161fee9a48
 		move is_dtype_supported logic to renderer (#14188) 
* move is_dtype_supported logic to renderer

* fix CPU_COUNT

* mypy happy

* early import libclang too with llvm

* run with debug

* skip autogen tests if MTLCompiler or llvm is loaded

* run autogen tests separately in CI

* lint
 2026-01-18 22:37:04 -05:00
qazal
7abe9b020f
 		viz: add border colors to pkts timeline (#14211) 
* viz: add border colors to pkts timeline

* 10
 2026-01-19 11:37:46 +09:00
chenyu
67d9712ef6
 		jit copy aliased output if it's read later (#14210) 2026-01-18 18:48:59 -05:00
chenyu
97333b1954
 		jit footguns test case on assign with same buffer outputs (#14209) 
related https://github.com/tinygrad/tinygrad/issues/13364
 2026-01-18 16:01:09 -05:00
chenyu
e7c2df9113
 		improve consecutive Tensor indexing (#14208) 
* improve consecutive Tensor indexing

instead of O(idx_counts*src_dims), it can just be O(idx_counts)

* test correctness
 2026-01-18 15:14:33 -05:00
chenyu
c7b8f6496f
 		remove dtypes.index_like and dtypes.fields [pr] (#14207) 
barely used, so just use inline and DTYPES_DICT
 2026-01-18 11:49:01 -05:00
qazal
e27a0002c5
 		viz: only keep the sqtt bytes for pkts (#14203) 
* viz: only keep the sqtt bytes for pkts

* better option name

* work

* renames
 2026-01-18 17:04:26 +09:00
qazal
d8f87ae2f2
 		SQTT packets to assembly mapper (#14198) 
* disasm + compare to llvm

* start inst trace

* base tests pass

* work

* work

* all kernels

* qol

* refactor

* work

* work

* wave_focus

* simple

* work

* add a lot of asserts

* focus on wave0

* correct handling of IMMEDIATE_MASK

* work

* viz work

* use the metadata infra

* better
 2026-01-18 16:32:13 +09:00
Christopher Milan
1eb110cd7d
 		fix memory corruption in NIR, reenable process replay (#14204) 2026-01-18 02:05:12 -05:00
George Hotz
a51e0a86db
 		assembly/amd: clean up disasm.py + add CDNA support (#14200) 
* assembly/amd: clean up disasm.py

* cleanups

* add missing encodings

* decode is pretty

* cdna

* assert on failure

* cdna roudtrip

* cdna passing

* test

* lil cleanup

* variant cleanups

* cleanups
 2026-01-18 14:48:44 +09:00
chenyu
4b18c92bc5
 		simpler Context.__enter__ [pr] (#14201) 2026-01-18 00:38:59 -05:00
qazal
feaa804158
 		skip lvp process replay in CI [pr] (#14202) 2026-01-18 13:25:04 +09:00
chenyu
b12a9fea80
 		runtime int call instead of cast(int) (#14183) 2026-01-17 20:34:45 -05:00
George Hotz
79c1559f69
 		amd asm can still be simpler (#14199) 
* amd asm can still be simpler

* simpler

* V_LANE_ID

* simpler

* simpler

* compact vgpr
 2026-01-17 18:40:10 +09:00
chenyu
5e6a72c33f
 		new Onnx Gather (#14187) 
instead of assuming const indices, check if it showed as a const
 2026-01-16 22:24:07 -05:00
George Hotz
9f7f2f0e0c MAX_SQTT_PKTS 2026-01-17 12:05:36 +09:00
George Hotz
50554115ee
 		fix VALU_SALU / IMMED_MASK and improve amd_asm_matmul (#14196) 
* fix VALU_SALU / IMMED_MASK and improve amd_asm_matmul

* immed

* wave override

* restore ALT

* advance sgprs correctly

* no helpers

* decrease to 192 VGPRs
 2026-01-17 11:58:34 +09:00
chenyu
ab244c7f81
 		onnx Gather should not assume indices to be const (#14185) 
* onnx Gather should not assume indices to be const

added a failed test case

* just list
 2026-01-16 20:55:00 -05:00
wozeparrot
a879b54234
 		tk: fa jit fix (#14170) 2026-01-16 16:38:45 -08:00
qazal
a8ae9757dd
 		viz: put alts in the same row, LDS color (#14194) 
* viz: put alts in the same row, coloring work

* assert if packets overlap

* lds color
 2026-01-17 09:36:14 +09:00
qazal
5aa71f437b
 		viz: precise clock cycles in PKTS (#14179) 
* viz: relative clock cycles in PKTS

* format clocks as xM yK 999 cycles
 2026-01-17 09:08:13 +09:00
Christopher Milan
eafcd44d95
 		fix OSX image pitch (#14193) 2026-01-16 19:07:33 -05:00
Christopher Milan
3960e2758c
 		suppress_finalizing in hip (#14189) 2026-01-16 18:56:29 -05:00
qazal
9302ab003a
 		viz: show ALT/OTHER packets on second lane (#14192) 
* viz: show dimmer ALT/OTHER packets

* remove todo comment

* work

* current vmem is gray
 2026-01-17 08:55:24 +09:00
qazal
551454f476
 		viz: fix wave sort, show message if sqtt trace is empty (#14190) 
* show message if sqtt trace is empty

* work

* fix wave sort

* back
 2026-01-17 08:01:26 +09:00
George Hotz
8a2549d42b
 		improve amd_asm_matmul + minor VIZ PKTS improvements (#14186) 
* improve amd_asm_matmul + minor VIZ PKTS improvements

* fix waitcnt issue

* cleanups
 2026-01-17 06:56:59 +09:00
George Hotz
7d1d9d4568
 		assembly/amd: remove IMG instruction support and asm.py (#14163) 
* assembly/amd: return IMG instruction supports

* remove asm.py

* op2dsl
 2026-01-17 06:21:50 +09:00
chenyu
dc4ae7dd08
 		lower ASSERT_MIN_STEP_TIME for driving_policy to 3ms (#14184) 
seems quite stable at 2.7ms now
 2026-01-16 15:04:53 -05:00
chenyu
0a14e1fcd4
 		fix some type ignore (#14182) 2026-01-16 13:56:45 -05:00
chenyu
fc10470883
 		add UOp.__index__ (#14181) 
Tensor slice is handled by __getitem__, so the index method is just for SupportsIndex
 2026-01-16 12:28:33 -05:00